/////////////////////////////////////////////////////
// File Name: frame_process.v
// Author: zeping fan
// mail:   zpfan007@163.com
// Created Time: 2023年06月27日 星期二 15时42分22秒
/////////////////////////////////////////////////////

module frame_process_tb();

reg             clk;
reg             rst_n;
reg             frame_mux_ptr_fifo_empty;
wire            frame_mux_ptr_fifo_rd;
reg     [15:0]  frame_mux_ptr_fifo_dout;
wire            frame_mux_data_fifo_rd;
reg     [7:0]   frame_mux_data_fifo_dout;

wire            se_source;
wire            se_req;
wire            se_mac;
wire            se_hash;
wire    [15:0]  se_portmap;
wire            se_ack;
wire            se_nak;
wire    [15:0]  se_result;

wire            queue_sof;
wire            queue_dv;
wire    [7:0]   queue_dout;


always #5   clk = ~clk;

initial begin
    $fsdbDumpfile("frame_process.fsdb");
    $fsdbDumpvars(0,frame_process_tb);
    $fsdbDumpMDA();
    
    clk = 1'b0;
    rst_n = 1'b0;
    frame_mux_ptr_fifo_empty = 1'b1;
    frame_mux_ptr_fifo_dout[15:0] = 16'b0;
    frame_mux_data_fifo_dout[7:0] = 8'b0;
    
    repeat(2)@(posedge clk);#0;
    rst_n = 1'b1;
    repeat(1050)@(posedge clk);#0;
    frame_mux_ptr_fifo_empty = 1'b0;
    write(
            16'b0001_0000_0100_0000,
            48'hf0f1f2f3f4f5,
            48'he0e1e2e3e4e5,
            16'h0800
    );
    #50000;
    frame_mux_ptr_fifo_empty = 1'b1;

    #20;
    $finish;
end



task    write();
    input   [15:0]  ptr;
    input   [47:0]  de_mac;
    input   [47:0]  so_mac;
    input   [15:0]  frame_type;
    
integer i;

begin
    while(frame_mux_ptr_fifo_rd)begin
        @(posedge clk);#0;
        frame_mux_ptr_fifo_dout[15:0] = ptr[15:0];
    end 
    
    while(frame_mux_data_fifo_rd)begin
        for(i=0;i<ptr[10:0];i=i+1)begin
            if(i==0)        frame_mux_data_fifo_dout[7:0] = de_mac[47:40];
            else if(i==1)   frame_mux_data_fifo_dout[7:0] = de_mac[39:32];
            else if(i==2)   frame_mux_data_fifo_dout[7:0] = de_mac[31:24];
            else if(i==3)   frame_mux_data_fifo_dout[7:0] = de_mac[23:16];
            else if(i==4)   frame_mux_data_fifo_dout[7:0] = de_mac[15:8];
            else if(i==5)   frame_mux_data_fifo_dout[7:0] = de_mac[7:0];
            else if(i==6)   frame_mux_data_fifo_dout[7:0] = so_mac[47:40];
            else if(i==7)   frame_mux_data_fifo_dout[7:0] = so_mac[39:32];
            else if(i==8)   frame_mux_data_fifo_dout[7:0] = so_mac[31:24];
            else if(i==9)   frame_mux_data_fifo_dout[7:0] = so_mac[23:16];
            else if(i==10)  frame_mux_data_fifo_dout[7:0] = so_mac[15:8];
            else if(i==11)  frame_mux_data_fifo_dout[7:0] = so_mac[7:0];
            else if(i==12)  frame_mux_data_fifo_dout[7:0] = frame_type[15:8];
            else if(i==13)  frame_mux_data_fifo_dout[7:0] = frame_type[7:0];
            else            frame_mux_data_fifo_dout[7:0] = i;
            @(posedge clk);#0;
        end
    end
end   
endtask



frame_process_v1
    x_frame_process(
        .clk(clk),
        .rst_n(rst_n),

//frame_mux interface
        .frame_mux_ptr_fifo_empty(frame_mux_ptr_fifo_empty),
        .frame_mux_ptr_fifo_rd(frame_mux_ptr_fifo_rd),
        .frame_mux_ptr_fifo_dout(frame_mux_ptr_fifo_dout),
        .frame_mux_data_fifo_rd(frame_mux_data_fifo_rd),
        .frame_mux_data_fifo_dout(frame_mux_data_fifo_dout),

//hash_lut interface
        .hash_lut_source(se_source),
        .hash_lut_req(se_req),
        .hash_lut_mac(se_mac),
        .hash_lut_hash(se_hash),
        .hash_lut_portmap(se_portmap),
        .hash_lut_ack(se_ack),
        .hash_lut_nak(se_nak),
        .hash_lut_result(se_result),

//queue_controller interface
        .queue_sof(queue_sof),
        .queue_dv(queue_dv),
        .queue_dout(queue_dout)
    );


hash_lut#(.TTL_NUM(4)
)
x_hash_lut(
.clk(clk),
.rst_n(rst_n),
.se_source(se_source),
.se_req(se_req),
.se_mac(se_mac),
.se_hash(se_hash),
.se_portmap(se_portmap),
.se_ack(se_ack),
.se_nak(se_nak),
.se_result(se_result),
.aging_req(1'b0),
.aging_ack()
);



endmodule
